| Presentation | 2009-02-16 A test pattern generation method to reduce the number of detected untestable faults on scan testing Masayoshi YOSHIMURA, Hiroshi OGAWA, Yusho OMORI, Toshinori HOSOKAWA, Kouji YAMAZAKI, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Scan testing is one of the most popular test method fo VLSIs. In this test, only information of the circuit structure is used, the circuit might be transferred to invalid state by the shift operations and be tested. Therefore, it is considered that scan testing is over testing. Over testing causes yield loss and the increase in number of test patterns. K cycle capture testing was proposed to decrease over testing. However, the test application time is long. In this paper, we propose a test pattern selection method for test application based on k cycle capture stuck-at test generation to reduce test application time. Our method also aim to reduce the number of detected untestable faults. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Over testing / Sequential circuit test generation / k-cycle capture test / Test pattern selection for test application |
| Paper # | DC2008-69 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2009/2/9(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A test pattern generation method to reduce the number of detected untestable faults on scan testing |
| Sub Title (in English) | |
| Keyword(1) | Over testing |
| Keyword(2) | Sequential circuit test generation |
| Keyword(3) | k-cycle capture test |
| Keyword(4) | Test pattern selection for test application |
| 1st Author's Name | Masayoshi YOSHIMURA |
| 1st Author's Affiliation | Graduate School of Infomation Science and Electrical Engineering, Kyushu University() |
| 2nd Author's Name | Hiroshi OGAWA |
| 2nd Author's Affiliation | Graduate School of Industrial Technology, Nihon University |
| 3rd Author's Name | Yusho OMORI |
| 3rd Author's Affiliation | Fugitsu Microerectronics |
| 4th Author's Name | Toshinori HOSOKAWA |
| 4th Author's Affiliation | Graduate School of Industrial Technology, Nihon University |
| 5th Author's Name | Kouji YAMAZAKI |
| 5th Author's Affiliation | School of Information and Communication, Meiji University |
| Date | 2009-02-16 |
| Paper # | DC2008-69 |
| Volume (vol) | vol.108 |
| Number (no) | 431 |
| Page | pp.pp.- |
| #Pages | 6 |
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