Presentation 2009/1/22
Design of Erase-Addressing Scheme on PDP According to the Number of Sustain Pulses before addressing
Seita IKEDA, Harimu SHIN, Tomokazu SHIGA,
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Abstract(in English) The multi-width scan pulse, erase-addressing scheme provides high speed and low voltage addressing. However the dynamic voltage margin is influenced by the number of sustain pulses before the addressing. In this report, the scan pulse widths were adjusted according to the number of sustain pulses for obtaining large margin. It was found that more than 19 sustain pulses are necessary when Full-HD PDP is driven with 24 contiguous-subfield, single-scan, 14 grouped AWD scheme. The width of scan pulse ranged from 0.2μs to 0.6μs with an average of 0.52μs. Driving with 3 sustain pulses is also possible when the number of groups is increased to 30 or the number of subfield is reduced to 19.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) plasma display / erase addressing / sustain pulse / dynamic voltage margin
Paper # EID2008-62
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Committee EID
Conference Date 2009/1/22(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Design of Erase-Addressing Scheme on PDP According to the Number of Sustain Pulses before addressing
Sub Title (in English)
Keyword(1) plasma display
Keyword(2) erase addressing
Keyword(3) sustain pulse
Keyword(4) dynamic voltage margin
1st Author's Name Seita IKEDA
1st Author's Affiliation Department of Electronic Engineering, The University of Electro-Communications()
2nd Author's Name Harimu SHIN
2nd Author's Affiliation Department of Electronic Engineering, The University of Electro-Communications
3rd Author's Name Tomokazu SHIGA
3rd Author's Affiliation Department of Electronic Engineering, The University of Electro-Communications
Date 2009/1/22
Paper # EID2008-62
Volume (vol) vol.108
Number (no) 421
Page pp.pp.-
#Pages 4
Date of Issue