講演名 | 2009/1/5 A Low Dynamic Power 90-nm CMOS Motion Estimation Processor Implementing Dynamic Voltage and Frequency Scaling Scheme and Fast Motion Estimation Algorithm Called Adaptively Assigned Breaking-off Condition Search(International Workshop on Advanced Image Technology 2009) , |
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抄録(英) | A 90-nm CMOS motion estimation(ME) processor was developed by employing dynamic voltage and frequency scaling (DVFS) to greatly reduce the dynamic power. To make full use of the advantages of DVFS, a fast ME algorithm and a small on-chip DC/DC converter were also developed. The fast ME algorithm can adaptively predict the optimum supply voltage (V_D) and the optimum clock frequency (f_c) before each block matching process starts. Power dissipation of the ME processor, which contained an absolute difference accumulator as well as the on-chip DC/DC converter and DVFS controller, was reduced to 31.5μW, which was only 2.8% that of a conventional ME processor. |
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キーワード(英) | H.264 / motion estimation / DVFS / power dissipation / DC/DC converter / PLL clock driver |
資料番号 | IE2008-180 |
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研究会情報 | |
研究会 | IE |
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開催期間 | 2009/1/5(から1日開催) |
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講演論文情報詳細 | |
申込み研究会 | Image Engineering (IE) |
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本文の言語 | ENG |
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サブタイトル(和) | |
タイトル(英) | A Low Dynamic Power 90-nm CMOS Motion Estimation Processor Implementing Dynamic Voltage and Frequency Scaling Scheme and Fast Motion Estimation Algorithm Called Adaptively Assigned Breaking-off Condition Search(International Workshop on Advanced Image Technology 2009) |
サブタイトル(和) | |
キーワード(1)(和/英) | / H.264 |
第 1 著者 氏名(和/英) | / Nobuaki Kobayashi |
第 1 著者 所属(和/英) | Chuo University, Graduate School of Science and Engineering Information and System Engineering Course |
発表年月日 | 2009/1/5 |
資料番号 | IE2008-180 |
巻番号(vol) | vol.108 |
号番号(no) | 373 |
ページ範囲 | pp.- |
ページ数 | 4 |
発行日 |