| Presentation | 2009-01-29 Fabrication of HTS-SQUIDs with multilayer structures and application to evaluation of YBCO coated conductors Seiji ADACHI, Hironori WAKANA, Kiyoshi HATA, Yasuo OSHIKUBO, Tsunehiro HATO, Yoshinobu TARUTANI, Keiichi TANABE, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We successfully fabricated SQUIDs with multilayer structures using high-T_c superconductors (HTS). Use of ramp-edge Josephson junctions enables us to make SQUIDs at desired positions in a chip. Employing multilayer structures, the devices can be arranged in a rather limited area. We fabricated a garadiometer array in a chip and investigated its feasibility for non-destructive evaluation of YBCO coated-conductors striated to achieve low AC-losses. A test piece comprising an upper Cu-tape and a lower YBCO thin film was prepared. When the piece was examined at ambient temperature, SQUID signals from defects in the Cu-tape were detected. On the other hand, signals from defects in YBCO were clearly observed when the piece was cooled at 77K. This indicated that defects in a Ag-stabilizing layer and a superconducting one can be detected separately by controlling the sample temperature. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Ramp-edge / Josephson junction / SQUID / Multilayer / YBCO coated conductor / Non-Destructive Evaluation |
| Paper # | SCE2008-39 |
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| Conference Information | |
| Committee | SCE |
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| Conference Date | 2009/1/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Chair | |
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| Paper Information | |
| Registration To | Superconductive Electronics (SCE) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Fabrication of HTS-SQUIDs with multilayer structures and application to evaluation of YBCO coated conductors |
| Sub Title (in English) | |
| Keyword(1) | Ramp-edge |
| Keyword(2) | Josephson junction |
| Keyword(3) | SQUID |
| Keyword(4) | Multilayer |
| Keyword(5) | YBCO coated conductor |
| Keyword(6) | Non-Destructive Evaluation |
| 1st Author's Name | Seiji ADACHI |
| 1st Author's Affiliation | SRL-ISTEC() |
| 2nd Author's Name | Hironori WAKANA |
| 2nd Author's Affiliation | SRL-ISTEC |
| 3rd Author's Name | Kiyoshi HATA |
| 3rd Author's Affiliation | SRL-ISTEC |
| 4th Author's Name | Yasuo OSHIKUBO |
| 4th Author's Affiliation | SRL-ISTEC |
| 5th Author's Name | Tsunehiro HATO |
| 5th Author's Affiliation | SRL-ISTEC |
| 6th Author's Name | Yoshinobu TARUTANI |
| 6th Author's Affiliation | SRL-ISTEC |
| 7th Author's Name | Keiichi TANABE |
| 7th Author's Affiliation | SRL-ISTEC |
| Date | 2009-01-29 |
| Paper # | SCE2008-39 |
| Volume (vol) | vol.108 |
| Number (no) | 420 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |