| Presentation | 2009-01-29 A Fast SIMD Processing Unit Synthesis Method with Optimal Pipeline Architecture for Application-specific Processors Takayuki WATANABE, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Small area, high performance and high productivity are required for application-specific processors in embedded systems. This paper proposes a fast SIMD processing unit synthesis method with optimal pipeline architecture applied to a processor core in hardware/software (HW/SW) co-synthesis system, SPADES, for application-specific processors. In the proposed method, if a pipelined SIMD processing unit with minimum delay is not on the critical path of a processor core, pipeline registers are inserted at optimal position which causes minimum amount of area increase within the critical path delay of a processor core. Therefore it can reduce area increase compared with the conventional method. Since this proposed method is fast to find the optimal solution, exploring processor architecture configuration is also effective. Finally, the SIMD operation unit generation system into which this proposed method is embeded generates HDL description of a SIMD processing unit. The experimental results show effectiveness of this method. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SIMD / Optimal Pipeline Architecture / HDL Generation Method / SPADES / Application-specific Processor |
| Paper # | VLD2008-108,CPSY2008-70,RECONF2008-72 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2009/1/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Fast SIMD Processing Unit Synthesis Method with Optimal Pipeline Architecture for Application-specific Processors |
| Sub Title (in English) | |
| Keyword(1) | SIMD |
| Keyword(2) | Optimal Pipeline Architecture |
| Keyword(3) | HDL Generation Method |
| Keyword(4) | SPADES |
| Keyword(5) | Application-specific Processor |
| 1st Author's Name | Takayuki WATANABE |
| 1st Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University() |
| 2nd Author's Name | Nozomu TOGAWA |
| 2nd Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University |
| 3rd Author's Name | Masao YANAGISAWA |
| 3rd Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University |
| 4th Author's Name | Tatsuo OHTSUKI |
| 4th Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University |
| Date | 2009-01-29 |
| Paper # | VLD2008-108,CPSY2008-70,RECONF2008-72 |
| Volume (vol) | vol.108 |
| Number (no) | 414 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |