| Presentation | 2009-01-29 Fast Module Placement in Floorplan-aware High-level Synthesis Wataru SATO, Akira OHCHI, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | As device feature size decreases, interconnect delay becomes the dominating factor of total delay. Therefore it is necessary to consider a floorplan in a stage of the high-level synthesis. While device feature size decreases, a condition of the Time to Market is severe, we need to design in a short time. Therefore it is desired to execute the high-level synthesis with floorplan in a short time. In this paper, we propose a high-speed module placement algorithm that used information of the high-level synthesis for the system that execute high-level synthesis and a floorplan repeatedly. This algorithm executes the placement fast that considered interconnect delay between modules by constructive method that used information of a scheduling/FU binding process. We show effectiveness of the proposed algorithm through experimental results. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | high level synthesis / floorplan / distributed-register architecture / conected-module infomation |
| Paper # | VLD2008-107,CPSY2008-69,RECONF2008-71 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2009/1/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Fast Module Placement in Floorplan-aware High-level Synthesis |
| Sub Title (in English) | |
| Keyword(1) | high level synthesis |
| Keyword(2) | floorplan |
| Keyword(3) | distributed-register architecture |
| Keyword(4) | conected-module infomation |
| 1st Author's Name | Wataru SATO |
| 1st Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University() |
| 2nd Author's Name | Akira OHCHI |
| 2nd Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University |
| 3rd Author's Name | Nozomu TOGAWA |
| 3rd Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University |
| 4th Author's Name | Masao YANAGISAWA |
| 4th Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University |
| 5th Author's Name | Tatsuo OHTSUKI |
| 5th Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University |
| Date | 2009-01-29 |
| Paper # | VLD2008-107,CPSY2008-69,RECONF2008-71 |
| Volume (vol) | vol.108 |
| Number (no) | 414 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |