Presentation 2009-01-29
FPGA Implementation of Metastability-based True Random Number Generator
Hisashi HATA, Shuichi ICHIKAWA,
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Abstract(in English) Metastability of RS latch is utilizable as an entropy source for true random number generators (TRNG). This kind of TRNG is comprised of logic gates, which can be integrated into a logic LSI. Though latch-based TRNG has been mostly implemented with full-custom LSI technology, this study presents an implementation with common FPGA technology. The RS latch in our TRNG is implemented as a hard-macro to guarantee the quality of randomness, minimizing the clock skew and load imbalance of internal nodes. The quality and throughput are further improved by XOR'ing the output of 32-128 latches. The derived design was implemented with Xilinx Virtex4 FPGA (XC4VFX20), and passed NIST test without post-processing. A TRNG of 128 latches occupies 290 slices, while achieving 8.33Mbps throughput.
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Keyword(in English) random number generator / synchronous digital circuit / FPGA / metastability
Paper # VLD2008-95,CPSY2008-57,RECONF2008-59
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Committee RECONF
Conference Date 2009/1/22(1days)
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Registration To Reconfigurable Systems (RECONF)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) FPGA Implementation of Metastability-based True Random Number Generator
Sub Title (in English)
Keyword(1) random number generator
Keyword(2) synchronous digital circuit
Keyword(3) FPGA
Keyword(4) metastability
1st Author's Name Hisashi HATA
1st Author's Affiliation Dept. Knowledge-based Information Engineering, Toyohashi University of Technology()
2nd Author's Name Shuichi ICHIKAWA
2nd Author's Affiliation Dept. Knowledge-based Information Engineering, Toyohashi University of Technology
Date 2009-01-29
Paper # VLD2008-95,CPSY2008-57,RECONF2008-59
Volume (vol) vol.108
Number (no) 414
Page pp.pp.-
#Pages 6
Date of Issue