Presentation 2009-01-29
Implementation and evaluation of arithmetic circuit for Poisson equation that aims at TFlops by using FPGA array
Kazuki SATO, Baatarsuren BARS, Masatoshi SEKINE,
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Abstract(in English) In recent years, the examples which use FPGA for the HPC use are increasing. We propose FPGA array which accumulated a lot of small cards with the three-dimensional I/O that installed large-scale FPGA. The FPGA array is suited to the scalable design, and it is possible to control from the host PC easily. In this paper, we implemented the arithmetic circuit which calculated Poisson equation by the finite difference method in floating point number into the FPGA array, and the performance and power consumption are presented. In addition, we have designed arithmetic circuits worked in parallel, and show a number of FPGA array to achieve 1[TFlops].
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Keyword(in English) FPGA / HPC / Scalable / hw/sw complex / Poisson equation
Paper # VLD2008-94,CPSY2008-56,RECONF2008-58
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Committee RECONF
Conference Date 2009/1/22(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Implementation and evaluation of arithmetic circuit for Poisson equation that aims at TFlops by using FPGA array
Sub Title (in English)
Keyword(1) FPGA
Keyword(2) HPC
Keyword(3) Scalable
Keyword(4) hw/sw complex
Keyword(5) Poisson equation
1st Author's Name Kazuki SATO
1st Author's Affiliation The Graduate School of Engineering, Tokyo University of Agriculture and Technology()
2nd Author's Name Baatarsuren BARS
2nd Author's Affiliation The Faculty of Engineering, Tokyo University of Agriculture and Technology
3rd Author's Name Masatoshi SEKINE
3rd Author's Affiliation The Graduate School of Engineering, Tokyo University of Agriculture and Technology
Date 2009-01-29
Paper # VLD2008-94,CPSY2008-56,RECONF2008-58
Volume (vol) vol.108
Number (no) 414
Page pp.pp.-
#Pages 6
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