Presentation 2009-01-29
Evaluation of a Multicore Reconfigurable Architecture
TUAN Vu MANH, Hiroki MATSUTANI, Naohiro KATSURA, Hideharu AMANO,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) A multicore reconfigurable architecture consisting of multiple small computational cores connected by an interconnection network is introduced. A comparision of a tile-based architecture and the proposed multicore architecture in terms of performance is examined. Then, an evaluation with different core sizes is implemented in order to find out how the size of cores in a homogeneous system influences on the performance and the internal fragmentation of target applications. Using real applications implemented on the proposed architecture in which cores are based on NEC Electronics' DRP-1, the evaluation result shows that the size of core is a trade-off between throughput and resource usage, and the size of two or three DRP tiles is an appropriate choice for many cases.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Multicore Reconfigurable Architecture / Tile-based Architecture / Core Size / Network-On-Chip
Paper # VLD2008-92,CPSY2008-54,RECONF2008-56
Date of Issue

Conference Information
Committee RECONF
Conference Date 2009/1/22(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To Reconfigurable Systems (RECONF)
Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Evaluation of a Multicore Reconfigurable Architecture
Sub Title (in English)
Keyword(1) Multicore Reconfigurable Architecture
Keyword(2) Tile-based Architecture
Keyword(3) Core Size
Keyword(4) Network-On-Chip
1st Author's Name TUAN Vu MANH
1st Author's Affiliation Graduate School of Science and Technology, Keio University()
2nd Author's Name Hiroki MATSUTANI
2nd Author's Affiliation Graduate School of Science and Technology, Keio University
3rd Author's Name Naohiro KATSURA
3rd Author's Affiliation Graduate School of Science and Technology, Keio University
4th Author's Name Hideharu AMANO
4th Author's Affiliation Graduate School of Science and Technology, Keio University
Date 2009-01-29
Paper # VLD2008-92,CPSY2008-54,RECONF2008-56
Volume (vol) vol.108
Number (no) 414
Page pp.pp.-
#Pages 6
Date of Issue