講演名 | 2009-01-29 Evaluation of a Multicore Reconfigurable Architecture , |
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PDFダウンロードページ | PDFダウンロードページへ |
抄録(和) | |
抄録(英) | A multicore reconfigurable architecture consisting of multiple small computational cores connected by an interconnection network is introduced. A comparision of a tile-based architecture and the proposed multicore architecture in terms of performance is examined. Then, an evaluation with different core sizes is implemented in order to find out how the size of cores in a homogeneous system influences on the performance and the internal fragmentation of target applications. Using real applications implemented on the proposed architecture in which cores are based on NEC Electronics' DRP-1, the evaluation result shows that the size of core is a trade-off between throughput and resource usage, and the size of two or three DRP tiles is an appropriate choice for many cases. |
キーワード(和) | |
キーワード(英) | Multicore Reconfigurable Architecture / Tile-based Architecture / Core Size / Network-On-Chip |
資料番号 | VLD2008-92,CPSY2008-54,RECONF2008-56 |
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研究会情報 | |
研究会 | RECONF |
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開催期間 | 2009/1/22(から1日開催) |
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講演論文情報詳細 | |
申込み研究会 | Reconfigurable Systems (RECONF) |
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本文の言語 | ENG |
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サブタイトル(和) | |
タイトル(英) | Evaluation of a Multicore Reconfigurable Architecture |
サブタイトル(和) | |
キーワード(1)(和/英) | / Multicore Reconfigurable Architecture |
第 1 著者 氏名(和/英) | / TUAN Vu MANH |
第 1 著者 所属(和/英) | Graduate School of Science and Technology, Keio University |
発表年月日 | 2009-01-29 |
資料番号 | VLD2008-92,CPSY2008-54,RECONF2008-56 |
巻番号(vol) | vol.108 |
号番号(no) | 414 |
ページ範囲 | pp.- |
ページ数 | 6 |
発行日 |