Presentation 2009-01-29
Implementation of Dynamically Reconfigurable Processor MuCCRA-3 and Methods for Reconfiguration Overhead Reduction
Toru SANO, Hideharu AMANO,
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Abstract(in English) We have developed and evaluated MuCCRA-1 and 2 in order to analyze architectural trade-off in dynamically reconfigurable processors. Here, we propose MuCCRA-3 which has higher performance, and works with low-power consumption based on the implementation and evaluation of MuCCRA-1,2. As a result of the evaluation, it appears that MuCCRA-3 achieves almost double performance as MuCCRA-1. Furthermore, we propose two methods to reduce the configuration data transfer cycles which may form a bottleneck of performance. The first method is called "Data Bus Configuration" that enables to transfer the configuration data through the data bus. And the other is "Fine-grained Partial Reconfiguration", which enables to reconfigure unit by unit. These methods reduce the configuration transfer cycle about 30%-50%.
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Keyword(in English) Dynamically Reconfigurable Processor / Reconfiguration / Overhead
Paper # VLD2008-91,CPSY2008-53,RECONF2008-55
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Committee RECONF
Conference Date 2009/1/22(1days)
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Registration To Reconfigurable Systems (RECONF)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Implementation of Dynamically Reconfigurable Processor MuCCRA-3 and Methods for Reconfiguration Overhead Reduction
Sub Title (in English)
Keyword(1) Dynamically Reconfigurable Processor
Keyword(2) Reconfiguration
Keyword(3) Overhead
1st Author's Name Toru SANO
1st Author's Affiliation Faculty of Science and Technology, Keio University()
2nd Author's Name Hideharu AMANO
2nd Author's Affiliation Faculty of Science and Technology, Keio University
Date 2009-01-29
Paper # VLD2008-91,CPSY2008-53,RECONF2008-55
Volume (vol) vol.108
Number (no) 414
Page pp.pp.-
#Pages 6
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