| Presentation | 2008-12-12 Optically Coupled Fail-safe Logic Gates Daichi KUDO, Yuji HIRAO, Tetsuya KIMURA, Koichi FUTSUHARA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Optically coupled fail-safe logic gates are proposed in this paper. Whereas the conventional fail-safe logic gates based on dynamic processing adopt level transformation by boosted voltage to avoid the influence of input malfunction to output, the proposed gates apply photocouplers to enhance the electronic independence of logic gate components. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Safety device / Fail-safe / Window Comparator / Optical Coupling / Photocoupler |
| Paper # | DC2008-59 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2008/12/5(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Optically Coupled Fail-safe Logic Gates |
| Sub Title (in English) | |
| Keyword(1) | Safety device |
| Keyword(2) | Fail-safe |
| Keyword(3) | Window Comparator |
| Keyword(4) | Optical Coupling |
| Keyword(5) | Photocoupler |
| 1st Author's Name | Daichi KUDO |
| 1st Author's Affiliation | Nagaoka University of Technology() |
| 2nd Author's Name | Yuji HIRAO |
| 2nd Author's Affiliation | Nagaoka University of Technology |
| 3rd Author's Name | Tetsuya KIMURA |
| 3rd Author's Affiliation | Nagaoka University of Technology |
| 4th Author's Name | Koichi FUTSUHARA |
| 4th Author's Affiliation | Nagaoka University of Technology |
| Date | 2008-12-12 |
| Paper # | DC2008-59 |
| Volume (vol) | vol.108 |
| Number (no) | 352 |
| Page | pp.pp.- |
| #Pages | 4 |
| Date of Issue | |