Presentation 2008-12-17
Power Analysis against an FPGA Implementation of the AES with SubBytes in a memory table
Hiroyuki KAWAKITA, Yusei NISHIMOTO, Kiyohiko ISHIKAWA, Hiroyuki IMAIZUMI,
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Abstract(in English) We have adopted a reconfigurable system as a receiver of Downloadable Conditional Access System (DCAS). DCAS involves a broadcasting company selecting and sending bitstream data of a hardware circuit. This paper shows a result of a comparison of two implementations of SubBytes in the 128bits-AES on SASEBO (Side-Channel Attack Standard Evaluation Board) in terms of resistance to a power analysis attack.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Downloadable CAS / AES / SASEBO / CPA
Paper # ISEC2008-100
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Conference Information
Committee ISEC
Conference Date 2008/12/10(1days)
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Paper Information
Registration To Information Security (ISEC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Power Analysis against an FPGA Implementation of the AES with SubBytes in a memory table
Sub Title (in English)
Keyword(1) Downloadable CAS
Keyword(2) AES
Keyword(3) SASEBO
Keyword(4) CPA
1st Author's Name Hiroyuki KAWAKITA
1st Author's Affiliation Science & Technical Research Laboratories, JAPAN BROADCASTING CORPORATION()
2nd Author's Name Yusei NISHIMOTO
2nd Author's Affiliation Science & Technical Research Laboratories, JAPAN BROADCASTING CORPORATION
3rd Author's Name Kiyohiko ISHIKAWA
3rd Author's Affiliation Science & Technical Research Laboratories, JAPAN BROADCASTING CORPORATION
4th Author's Name Hiroyuki IMAIZUMI
4th Author's Affiliation Science & Technical Research Laboratories, JAPAN BROADCASTING CORPORATION
Date 2008-12-17
Paper # ISEC2008-100
Volume (vol) vol.108
Number (no) 355
Page pp.pp.-
#Pages 6
Date of Issue