| Presentation | 2008-11-18 An Adaptive Pattern Recognition hardware with On-chip Dynamic and Partial Reconfiguration H. KAWAI, Y. YAMAGUCHI, M. YASUNAGA, K. GLETTE, J. TORESSEN, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A pattern recognition system that can process a large amount of image data at high speed is required in many fields. In this paper, we propose an on-chip pattern recognition system that utilizes the reconfigurability of the FPGA. The features of the system are not only very high recognition speed but also an adaptive function. For example, when objects to be detected change appearance, recognition parameters must be changed to retain the recognition accuracy. The system can automatically adjust by executing on-chip partial reconfiguration. The system runs at 25MHz and can return a recognition result in one clock cycle, 40ns. To update the system, all processes needed for searching for the best recognition parameters, generating configuration data and reconfiguring the system are carried out within 30s. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / Partial and Dynamic Reconfiguration / Adaptive Hardware / Pattern Recognition |
| Paper # | RECONF2008-50 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2008/11/10(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Adaptive Pattern Recognition hardware with On-chip Dynamic and Partial Reconfiguration |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | Partial and Dynamic Reconfiguration |
| Keyword(3) | Adaptive Hardware |
| Keyword(4) | Pattern Recognition |
| 1st Author's Name | H. KAWAI |
| 1st Author's Affiliation | Graduate school of Systems and Information Engineering, University of Tsukuba() |
| 2nd Author's Name | Y. YAMAGUCHI |
| 2nd Author's Affiliation | Graduate school of Systems and Information Engineering, University of Tsukuba |
| 3rd Author's Name | M. YASUNAGA |
| 3rd Author's Affiliation | Graduate school of Systems and Information Engineering, University of Tsukuba |
| 4th Author's Name | K. GLETTE |
| 4th Author's Affiliation | Department of Informatics, University of Oslo |
| 5th Author's Name | J. TORESSEN |
| 5th Author's Affiliation | Department of Informatics, University of Oslo |
| Date | 2008-11-18 |
| Paper # | RECONF2008-50 |
| Volume (vol) | vol.108 |
| Number (no) | 300 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |