Presentation 2008-11-17
Inter-FPGA communication mechanism of FPGA-array for high-performance difference scheme computation
LUZHOU WANG, Kentaro SANO, Yoshiaki HATSUDA, Satoru YAMAMOTO,
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Abstract(in English) We propose array-structured custom-computing machines for high-performance difference scheme computation. The performance of the machines is in proportion to the number of PEs, because of the array structure of PEs. To achieve higher performance, we are implementing a large PE-array with an FPGA-array consisting of a lot of FPGAs. For the FPGA-array, the bandwidth between FPGAs limits the overall performance. In this paper, we show that actual computation requires narrower bandwidth than the full bandwidth due to sparse data-transer requirement. And then, we present a hardware structure to exploit the sparse data-transfer for narrower bandwidth in the inter-FPGA communication.
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Keyword(in English) custom computing machines / difference scheme / FPGA / I/O bandwidth
Paper # RECONF2008-46
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Committee RECONF
Conference Date 2008/11/10(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Inter-FPGA communication mechanism of FPGA-array for high-performance difference scheme computation
Sub Title (in English)
Keyword(1) custom computing machines
Keyword(2) difference scheme
Keyword(3) FPGA
Keyword(4) I/O bandwidth
1st Author's Name LUZHOU WANG
1st Author's Affiliation Graduate School of Information Sciences, Tohoku University()
2nd Author's Name Kentaro SANO
2nd Author's Affiliation Graduate School of Information Sciences, Tohoku University
3rd Author's Name Yoshiaki HATSUDA
3rd Author's Affiliation Graduate School of Information Sciences, Tohoku University
4th Author's Name Satoru YAMAMOTO
4th Author's Affiliation Graduate School of Information Sciences, Tohoku University
Date 2008-11-17
Paper # RECONF2008-46
Volume (vol) vol.108
Number (no) 300
Page pp.pp.-
#Pages 4
Date of Issue