Presentation | 2008-11-17 Soft Error Mitigation Techniques for FPGA Switch Matrices Yuki KOU, Masaki NAKANISHI, Shigeru YAMASHITA, Yasuhiko NAKASHIMA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Recentry, a soft error becomes a serious probrem as the process shrinking. Especially, SRAMs seriously suffer from a soft error, and thus various techniques have been proposed to deal with it. In this paper, we propose a technique to utilize ASRAM for the memory cells to control the pass transistors in an SRAM based FPGAs. We confirmed that the proposed techniques have high error tolerance than that of TMR when the ratio of 0's in the configuration bits are larger than some constant value. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Soft error / SRAM-based FPGA / Pass Transister / TMR |
Paper # | RECONF2008-45 |
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Committee | RECONF |
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Conference Date | 2008/11/10(1days) |
Place (in Japanese) | (See Japanese page) |
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Registration To | Reconfigurable Systems (RECONF) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Soft Error Mitigation Techniques for FPGA Switch Matrices |
Sub Title (in English) | |
Keyword(1) | Soft error |
Keyword(2) | SRAM-based FPGA |
Keyword(3) | Pass Transister |
Keyword(4) | TMR |
1st Author's Name | Yuki KOU |
1st Author's Affiliation | Nara Institute of Science and Technology() |
2nd Author's Name | Masaki NAKANISHI |
2nd Author's Affiliation | Nara Institute of Science and Technology |
3rd Author's Name | Shigeru YAMASHITA |
3rd Author's Affiliation | Nara Institute of Science and Technology |
4th Author's Name | Yasuhiko NAKASHIMA |
4th Author's Affiliation | Nara Institute of Science and Technology |
Date | 2008-11-17 |
Paper # | RECONF2008-45 |
Volume (vol) | vol.108 |
Number (no) | 300 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |