Presentation 2008-11-17
Hardware Implementation Costs of Adaptive Routing in the Hierarchical Interconnection Network
Masahiro Kaneko, Yasuyuki Miura, Shigeyoshi Watanabe,
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Abstract(in English) By progress of VLSI technology, "On-Chip-Multiprocessor" which processes in parallel on a wafer has been realized, and a hierarchical interconnection network TESH was proposed. Three types of adaptive routing algorithms of TESH were proposed and their availability was verified by software simulation. However, it has not verified about the increase of the hardware cost and delay. In this paper, the two types of adaptive routing algorithms of TESH (the CS algorithm and the LS algorithm) are designed by VHDL and the delay and hardware cost are evaluated.
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Keyword(in English) Interconnection Network / TESH / Routing Algorithm
Paper # RECONF2008-44
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Conference Information
Committee RECONF
Conference Date 2008/11/10(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Hardware Implementation Costs of Adaptive Routing in the Hierarchical Interconnection Network
Sub Title (in English)
Keyword(1) Interconnection Network
Keyword(2) TESH
Keyword(3) Routing Algorithm
1st Author's Name Masahiro Kaneko
1st Author's Affiliation Shonan Institute of Technology()
2nd Author's Name Yasuyuki Miura
2nd Author's Affiliation Shonan Institute of Technology
3rd Author's Name Shigeyoshi Watanabe
3rd Author's Affiliation Shonan Institute of Technology
Date 2008-11-17
Paper # RECONF2008-44
Volume (vol) vol.108
Number (no) 300
Page pp.pp.-
#Pages 6
Date of Issue