| Presentation | 2008-11-18 Generation of High Coverage Property Set Using Counterexamples Takeshi MATSUMOTO, Yeonbok LEE, Hiroaki YOSHIDA, Hisashi YOMIYA, Masahiro FUJITA, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | When we design a large system including hardware and software, verification in specification-level is very important to avoid design bugs from the subsequent design-levels such as system-level and behavior-level. However, partly because the specification documents itself has unclarity and ambiguity, correctly writing properties to be kept in designs is difficult. In this work, we propose a high-level design flow considering verification and property derivation in that flow. In general, the quality of property checking is decided by the completeness of a set of given properties. Therefore, metrics to measure the completeness of the property set and methods to generate properties with high completeness are required. We propose a transition-based coverage metric that is defined in finite state machine of the system specification. Through a case study of an elevator controller design, we also show a way to generate properties that can improve the coverage from counterexamples found in simulation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Specification / High-level design / Formal verification / Property checking / UML |
| Paper # | VLD2008-79,DC2008-47 |
| Date of Issue |
| Conference Information | |
| Committee | DC |
|---|---|
| Conference Date | 2008/11/10(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Dependable Computing (DC) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Generation of High Coverage Property Set Using Counterexamples |
| Sub Title (in English) | |
| Keyword(1) | Specification |
| Keyword(2) | High-level design |
| Keyword(3) | Formal verification |
| Keyword(4) | Property checking |
| Keyword(5) | UML |
| 1st Author's Name | Takeshi MATSUMOTO |
| 1st Author's Affiliation | VLSI Design and Education Center, University of Tokyo() |
| 2nd Author's Name | Yeonbok LEE |
| 2nd Author's Affiliation | Dept. of Electrical Engineering and Information Systems, University of Tokyo |
| 3rd Author's Name | Hiroaki YOSHIDA |
| 3rd Author's Affiliation | VLSI Design and Education Center, University of Tokyo |
| 4th Author's Name | Hisashi YOMIYA |
| 4th Author's Affiliation | Corporate Software Engineering Center, Toshiba Corporation |
| 5th Author's Name | Masahiro FUJITA |
| 5th Author's Affiliation | VLSI Design and Education Center, University of Tokyo |
| Date | 2008-11-18 |
| Paper # | VLD2008-79,DC2008-47 |
| Volume (vol) | vol.108 |
| Number (no) | 299 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |