| Presentation | 2008-11-18 Evaluation of Hardware Algorithms on a Circuit Model Considering Wire Delay Tetsuya NAGASE, Kazuyoshi TAKAGI, Naofumi TAKAGI, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In the design of integrated circuits, it is important to design or choose algorithms according to the requirements such as the computation time and area. In the conservative logic circuit model, the computation time of hardware algorithms are evaluated by the circuit depth, and the wire delay has been ignored. However, with the recent miniaturization of the integrated circuits, the wire delay become significant and cannot be ignored relative to the delay of the logic elements. Therefore, the more realistic circuit model considering the wire delay is necessary. In this report, we propose a circuit model which assumes that the wire delay depends on its length. We evaluate computation time of several hardware algorithms. As a result, we could find that the effect of the wire delay grows in the circuit with small circuit depth. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | wire delay / hardware algorithm / circuit model / parallel multiplier / parallel adder |
| Paper # | VLD2008-77,DC2008-45 |
| Date of Issue |
| Conference Information | |
| Committee | DC |
|---|---|
| Conference Date | 2008/11/10(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Dependable Computing (DC) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Evaluation of Hardware Algorithms on a Circuit Model Considering Wire Delay |
| Sub Title (in English) | |
| Keyword(1) | wire delay |
| Keyword(2) | hardware algorithm |
| Keyword(3) | circuit model |
| Keyword(4) | parallel multiplier |
| Keyword(5) | parallel adder |
| 1st Author's Name | Tetsuya NAGASE |
| 1st Author's Affiliation | Graduate School of Information Science, Nagoya University() |
| 2nd Author's Name | Kazuyoshi TAKAGI |
| 2nd Author's Affiliation | Graduate School of Information Science, Nagoya University |
| 3rd Author's Name | Naofumi TAKAGI |
| 3rd Author's Affiliation | Graduate School of Information Science, Nagoya University |
| Date | 2008-11-18 |
| Paper # | VLD2008-77,DC2008-45 |
| Volume (vol) | vol.108 |
| Number (no) | 299 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |