Presentation 2008-11-18
A Two-level Cache and Scratch Pad Memory Simulation for Embedded Systems
Nobuaki TOJO, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI,
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Abstract(in English) In an embedded system where a single application or a class of applications are repeatedly executed on a processor, its memory configuration can be customized such that an optimal one is achieved. We can have an optimal two-level cache and scratch pad memory configuration which minimizes overall memory access time or energy consumption by varying the seven parameters: the number of sets of an L1/L2 cache, a line size of an L1/L2 cache, an associativity of an L1/L2 cache, and a size of a scratch pad memory. In this paper, we propose two-level cache and scratch pad memory design space exploration algorithms: CRCB-T and CRCB-S. Our proposed approach totally runs a maximum of 3172.94 faster compared to the conventional exhaustive approach.
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Keyword(in English) cache / two-level cache / scratch pad memory / cache simulation / cache optimization / embedded system
Paper # VLD2008-76,DC2008-44
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Committee DC
Conference Date 2008/11/10(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Two-level Cache and Scratch Pad Memory Simulation for Embedded Systems
Sub Title (in English)
Keyword(1) cache
Keyword(2) two-level cache
Keyword(3) scratch pad memory
Keyword(4) cache simulation
Keyword(5) cache optimization
Keyword(6) embedded system
1st Author's Name Nobuaki TOJO
1st Author's Affiliation Dept. of Computer Science and Engineering, Waseda University()
2nd Author's Name Nozomu TOGAWA
2nd Author's Affiliation Dept. of Computer Science and Engineering, Waseda University
3rd Author's Name Masao YANAGISAWA
3rd Author's Affiliation Dept. of Computer Science and Engineering, Waseda University
4th Author's Name Tatsuo OHTSUKI
4th Author's Affiliation Dept. of Computer Science and Engineering, Waseda University
Date 2008-11-18
Paper # VLD2008-76,DC2008-44
Volume (vol) vol.108
Number (no) 299
Page pp.pp.-
#Pages 6
Date of Issue