Presentation 2008-11-17
Evaluating the reliability of Highly Reliable Cell Circuits
Keiichi HOTTA, Takashi NAKADA, Masaki NAKANISHI, Shigeru YAMASHITA, Yasuhiko NAKASHIMA,
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Abstract(in English) Recently, the shrinking process causes transistor variation and growth of error rate. Highly Reliable Cells (HRCs) have been proposed to solve these problems. We need to evaluate reliability of them quantitatively, because they are considered to be highly reliable. Although, there have been proposed several methods to evaluate the reliability, they cannot evaluate the reliability of circuits by HRCs accurately. Therefore, in this paper, we propose a new evaluation method for the reliability of circuits based on the fault probability of each transistor. The method can evaluate the reliablity of circuits by HRCs or the CMOS cells. The experimental results show that HRCs are more reliable than the CMOS cells.
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Keyword(in English) reliability evaluation / fault tolerance / transistor variation
Paper # VLD2008-75,DC2008-43
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Committee DC
Conference Date 2008/11/10(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Evaluating the reliability of Highly Reliable Cell Circuits
Sub Title (in English)
Keyword(1) reliability evaluation
Keyword(2) fault tolerance
Keyword(3) transistor variation
1st Author's Name Keiichi HOTTA
1st Author's Affiliation Nara Institute of Science and Technology()
2nd Author's Name Takashi NAKADA
2nd Author's Affiliation Nara Institute of Science and Technology
3rd Author's Name Masaki NAKANISHI
3rd Author's Affiliation Nara Institute of Science and Technology
4th Author's Name Shigeru YAMASHITA
4th Author's Affiliation Nara Institute of Science and Technology
5th Author's Name Yasuhiko NAKASHIMA
5th Author's Affiliation Nara Institute of Science and Technology
Date 2008-11-17
Paper # VLD2008-75,DC2008-43
Volume (vol) vol.108
Number (no) 299
Page pp.pp.-
#Pages 6
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