Presentation 2008-11-17
A Parallel Hardware Engine for Generating Deformed Maps
Akira ARAHATA, Ryuta NARA, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) Recently, many of the distribution of map information to mobile devices have been highly-popularized, however, those maps are generally for PC use and not suitable for displays as on mobile devices. According to the nature of map information, it has to be updated in real time, it is a distant idea to prepare an easy-to-read deformed map in advance. For that reason, it is difficult to tailor deformed map to preference of user when processing map on servers even automatic deformation of map data is proposed numerously. Mobile devices need loads of processing time which is virtually impossible in attribute to massive processing volume of data has to be required to deform map data by narrow throughput of mobile devices. In this paper, we propose parallel processing hardware engine for map deformation for mobile devices. We worked out to reduce processing time by processing on hardwares which was bottleneck of map deformation. Proposed parallel processing hardware engine can process deformation of map data within just 1 second on a mobile phone.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) deformed map / mobile phone / parallel processing / hardware design
Paper # VLD2008-67,DC2008-35
Date of Issue

Conference Information
Committee DC
Conference Date 2008/11/10(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Parallel Hardware Engine for Generating Deformed Maps
Sub Title (in English)
Keyword(1) deformed map
Keyword(2) mobile phone
Keyword(3) parallel processing
Keyword(4) hardware design
1st Author's Name Akira ARAHATA
1st Author's Affiliation Dept. of Computer Science and Engineering, Waseda University()
2nd Author's Name Ryuta NARA
2nd Author's Affiliation Dept. of Computer Science and Engineering, Waseda University
3rd Author's Name Nozomu TOGAWA
3rd Author's Affiliation Dept. of Computer Science and Engineering, Waseda University
4th Author's Name Masao YANAGISAWA
4th Author's Affiliation Dept. of Computer Science and Engineering, Waseda University
5th Author's Name Tatsuo OHTSUKI
5th Author's Affiliation Dept. of Computer Science and Engineering, Waseda University
Date 2008-11-17
Paper # VLD2008-67,DC2008-35
Volume (vol) vol.108
Number (no) 299
Page pp.pp.-
#Pages 6
Date of Issue