Presentation 2008-11-17
Area Efficient Multipliers Utilizing the Sum of Operands
Hirotaka KAWASHIMA, Naofumi TAKAGI,
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Abstract(in English) A method to halve the number of partial product bits in multiplication is proposed. An integrated partial product (IPP) is introduced. The method separates the IPP into four cases. Each case is represented in half the number of the original partial product bits by utilizing the sum of the operands. The value of the IPP is obtained by selecting a value from the four cases. The proposed method is applicable to both unsigned and signed multiplication. Multipliers using the proposed method are smaller than array multipliers and Wallace multipliers by approximately 30%, and smaller than multipliers with radix-4 Booth's method by approximately 10%.
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Keyword(in English) VLSI / arithmetic circuit / multiplication
Paper # VLD2008-64,DC2008-32
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Committee DC
Conference Date 2008/11/10(1days)
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Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Area Efficient Multipliers Utilizing the Sum of Operands
Sub Title (in English)
Keyword(1) VLSI
Keyword(2) arithmetic circuit
Keyword(3) multiplication
1st Author's Name Hirotaka KAWASHIMA
1st Author's Affiliation Department of Information Engineering, Graduate School of Information Science, Nagoya University()
2nd Author's Name Naofumi TAKAGI
2nd Author's Affiliation Department of Information Engineering, Graduate School of Information Science, Nagoya University
Date 2008-11-17
Paper # VLD2008-64,DC2008-32
Volume (vol) vol.108
Number (no) 299
Page pp.pp.-
#Pages 6
Date of Issue