| Presentation | 2008-11-19 Leakage Power Reduction Method for Dual-Rail Four-Phase Asynchronous Circuits Using Multi-Vth Transistors Koei TAKADA, Masashi IMAI, Hiroshi NAKAMURA, Takashi NANYA, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Dual-rail four-phase asynchronous circuits are well-known for their benefits in terms of delay variation tolerance. On the other hand, dual-rail circuits need to reduce their leakage power, since dual-rail asynchronous logic is often known to be larger than its equivalent single-rail counter-part, and thus its leakage power is also larger. In this paper, we propose leakage power reduction method for dual-rail four-phase asynchronous circuits using multi-Vth transistors. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Delay Variation / Leakage Power / Dual-rail Four-Phase Asynchronous Circuit / Multi-Vth Transistor |
| Paper # | VLD2008-90,DC2008-58 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2008/11/10(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Leakage Power Reduction Method for Dual-Rail Four-Phase Asynchronous Circuits Using Multi-Vth Transistors |
| Sub Title (in English) | |
| Keyword(1) | Delay Variation |
| Keyword(2) | Leakage Power |
| Keyword(3) | Dual-rail Four-Phase Asynchronous Circuit |
| Keyword(4) | Multi-Vth Transistor |
| 1st Author's Name | Koei TAKADA |
| 1st Author's Affiliation | Reserch Center for Advanced Science and Technology, The University of Tokyo() |
| 2nd Author's Name | Masashi IMAI |
| 2nd Author's Affiliation | Reserch Center for Advanced Science and Technology, The University of Tokyo |
| 3rd Author's Name | Hiroshi NAKAMURA |
| 3rd Author's Affiliation | Reserch Center for Advanced Science and Technology, The University of Tokyo |
| 4th Author's Name | Takashi NANYA |
| 4th Author's Affiliation | Reserch Center for Advanced Science and Technology, The University of Tokyo |
| Date | 2008-11-19 |
| Paper # | VLD2008-90,DC2008-58 |
| Volume (vol) | vol.108 |
| Number (no) | 298 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |