| Presentation | 2008-11-19 An On-Chip Decoupling Capacitance Budgeting Methodology by Using Power-Capacitance Ratio Susumu KOBAYASHI, Naoshi DOI, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The high-speed and low-power system LSIs in recent years have crucial need for managing power supply noise so that it might not substantially affect the circuit functionality and performance. The decoupling capacitance is known as an effective measure for suppressing the power supply noise. In this paper, we propose a design methodology for decoupling capacitance budgeting, in which the decoupling capacitance is distributed appropriately over the LSI chip area in order to suppress the power supply noise of each local region. For efficient budgeting, we introduced a new concept of power-capacitance ratio, which is the ratio of power dissipation to capacitance. The proposed method first performs a simplified power supply noise analysis by using a lumped circuit model to determine the total required on-chip capacitance, and calculate the power-capacitance ratio. Then, in the layout design phase, the decoupling capacitance budgeting is performed by using the above power-capacitance ratio as a guideline. The effectiveness of the proposed method was verified by using SPICE simulations on example chip models of 90nm technology node. The verification results show that, even for a chip with very wide on-chip variation in power density, the proposed method can suppress the power supply noise of each local region effectively. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Decoupling Capacitance / Power Supply Noise / Power Dissipation / Layout Design / Simulation |
| Paper # | CPM2008-95,ICD2008-94 |
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| Conference Information | |
| Committee | CPM |
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| Conference Date | 2008/11/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Component Parts and Materials (CPM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An On-Chip Decoupling Capacitance Budgeting Methodology by Using Power-Capacitance Ratio |
| Sub Title (in English) | |
| Keyword(1) | Decoupling Capacitance |
| Keyword(2) | Power Supply Noise |
| Keyword(3) | Power Dissipation |
| Keyword(4) | Layout Design |
| Keyword(5) | Simulation |
| 1st Author's Name | Susumu KOBAYASHI |
| 1st Author's Affiliation | NEC Electronics Corporation() |
| 2nd Author's Name | Naoshi DOI |
| 2nd Author's Affiliation | NEC Electronics Corporation |
| Date | 2008-11-19 |
| Paper # | CPM2008-95,ICD2008-94 |
| Volume (vol) | vol.108 |
| Number (no) | 301 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |