Presentation 2008-11-19
A Fast Simulation Technique of Processor Power Supply Noise using Capacitance Charging Model
Fukuichi IWASA, Takuya SAWADA, Mitsuya FUKAZAWA, Makoto NAGATA,
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Abstract(in English) A fast simulation technique is proposed for the power supply noise analysis of the large-scale digital processor. The analysis cost is improved by reducing the scale of capacitance charging model with capacitance statistics data. The proposed technique is applied to a test chip fabricated with a 90nm CMOS process technology and shortens analysis time 62.8% at the maximum at the maintained precision.
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Keyword(in English) Power supply noise / Capacitance charging model / SRAM model / Noise analysis
Paper # CPM2008-94,ICD2008-93
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Committee CPM
Conference Date 2008/11/11(1days)
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Registration To Component Parts and Materials (CPM)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Fast Simulation Technique of Processor Power Supply Noise using Capacitance Charging Model
Sub Title (in English)
Keyword(1) Power supply noise
Keyword(2) Capacitance charging model
Keyword(3) SRAM model
Keyword(4) Noise analysis
1st Author's Name Fukuichi IWASA
1st Author's Affiliation Graduate School of Technology, Kobe University()
2nd Author's Name Takuya SAWADA
2nd Author's Affiliation Graduate School of Technology, Kobe University
3rd Author's Name Mitsuya FUKAZAWA
3rd Author's Affiliation Graduate School of Technology, Kobe University
4th Author's Name Makoto NAGATA
4th Author's Affiliation Graduate School of Technology, Kobe University
Date 2008-11-19
Paper # CPM2008-94,ICD2008-93
Volume (vol) vol.108
Number (no) 301
Page pp.pp.-
#Pages 6
Date of Issue