Presentation	2008-11-18 LSI, PCB Co-analysis Technology Toshiro Sato,
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Abstract(in Japanese)	(See Japanese page)
Abstract(in English)	Increase of digital equipment operation frequency and decrease of LSI supply voltage are causing the emerging problem of ground bounce noise, simultaneous switching noise and EMI noise. We have developed a system that enables us to optimize the noise countermeasure designs by performing the large scale simulation unifying LSI and PCB at the design stages from upper design stage to the verification stage of final design. This system has been applied to the designs and the redesigns caused by noise problems are eradicated. In this paper, the features of the system and results and effectiveness of the application are explained.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	Voltage ground bounce noise / Simultaneous switching noise / PEEC Method / EMI / Circuit simulation
Paper #	CPM2008-92,ICD2008-91
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Conference Information
Committee	CPM
Conference Date	2008/11/11(1days)
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Paper Information
Registration To	Component Parts and Materials (CPM)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	LSI, PCB Co-analysis Technology
Sub Title (in English)
Keyword(1)	Voltage ground bounce noise
Keyword(2)	Simultaneous switching noise
Keyword(3)	PEEC Method
Keyword(4)	EMI
Keyword(5)	Circuit simulation
1st Author's Name	Toshiro Sato
1st Author's Affiliation	Fujitsu Advanced Technologies Limited()
Date	2008-11-18
Paper #	CPM2008-92,ICD2008-91
Volume (vol)	vol.108
Number (no)	301
Page	pp.pp.-
#Pages	6
Date of Issue