| Presentation | 2008-11-18 Optimization of Power Integrity in Packaging Design for a High-Performance Microprocessor Shin SUMINAGA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | High performance, low power consumption, and high manufacturing yield are crucial factors of a high-performance microprocessor. Those are mutually exclusive. In the mean time, characteristics of power distribution network (PDN) for the microprocessor chip, package, and system board make significant impacts on those factors. In this paper, the relationship among those factors is discussed. Also, a design and simulation methodologies to optimize the power integrity of the PDN used for Cell Broadband Engine^ |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Microprocessor / Power / TDP / PDN / Power Integrity / PI |
| Paper # | CPM2008-90,ICD2008-89 |
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| Conference Information | |
| Committee | CPM |
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| Conference Date | 2008/11/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Component Parts and Materials (CPM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Optimization of Power Integrity in Packaging Design for a High-Performance Microprocessor |
| Sub Title (in English) | |
| Keyword(1) | Microprocessor |
| Keyword(2) | Power |
| Keyword(3) | TDP |
| Keyword(4) | PDN |
| Keyword(5) | Power Integrity |
| Keyword(6) | PI |
| 1st Author's Name | Shin SUMINAGA |
| 1st Author's Affiliation | Microelectronics Division, IBM Japan() |
| Date | 2008-11-18 |
| Paper # | CPM2008-90,ICD2008-89 |
| Volume (vol) | vol.108 |
| Number (no) | 301 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |