| Presentation | 2008-10-31 Consideration of MPLD Architecture for High Performance Computing Tetsuo HIRONAKA, Naoki HIRAKAWA, Masanori YOSHIHARA, Kazuya TANIGAWA, Masayuki SATO, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | As the practical use of high performance FPGA increases, research on using FPGAs in the field of HPC (High Performance Computing) for scientific calculation is recently increasing. In contrast to the high-speed operation frequency of CPU, the configuration speed of FPGA is quite slow, which cause a serious overhead by the difference of CPU processing time and FPGA configuration time on HPC. Also in general, arithmetic operations in the FPGA and data in memory are separated by external I/Os which arises overhead for executing highly parallel operation in the FPGA. To avoid the overheads, we present a FPGA which can be partially reconfigured by the same action used for writing data in a memory, and also present the possibility for an FPGA for accessing memory without using external I/Os for reading and writing results of arithmetic operation done in the FPGA. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA architecture / configuration / partial configuration |
| Paper # | CPSY2008-31 |
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| Conference Information | |
| Committee | CPSY |
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| Conference Date | 2008/10/24(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Computer Systems (CPSY) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Consideration of MPLD Architecture for High Performance Computing |
| Sub Title (in English) | |
| Keyword(1) | FPGA architecture |
| Keyword(2) | configuration |
| Keyword(3) | partial configuration |
| 1st Author's Name | Tetsuo HIRONAKA |
| 1st Author's Affiliation | Graduated School of Information Sciences, Hiroshima City University() |
| 2nd Author's Name | Naoki HIRAKAWA |
| 2nd Author's Affiliation | Graduated School of Information Sciences, Hiroshima City University |
| 3rd Author's Name | Masanori YOSHIHARA |
| 3rd Author's Affiliation | Graduated School of Information Sciences, Hiroshima City University:(Present office)Renesas Technology Corp. |
| 4th Author's Name | Kazuya TANIGAWA |
| 4th Author's Affiliation | Graduated School of Information Sciences, Hiroshima City University |
| 5th Author's Name | Masayuki SATO |
| 5th Author's Affiliation | Taiyo Yuden Co., Ltd. |
| Date | 2008-10-31 |
| Paper # | CPSY2008-31 |
| Volume (vol) | vol.108 |
| Number (no) | 273 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |