| Presentation | 2008-10-07 On exact estimation of logic masking effect for soft erros on combinational circuits Yusuke MATSUNAGA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Soft-error is a phenomena that the output value of a logic gate flips transiently because of neutron particle strike, etc. In combinational circuit, not every soft error affects the behavior of the external outputs because of some masking effects. This paper proposes an efficient algorithm which exactly estimates the logic masking effect. This algorithm utilizes the previously computed results effectively to accelerate the entire computation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | soft error / combinational circuit / logic masking / fault simulation |
| Paper # | SIP2008-116,IE2008-80 |
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| Conference Information | |
| Committee | IE |
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| Conference Date | 2008/9/29(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Image Engineering (IE) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | On exact estimation of logic masking effect for soft erros on combinational circuits |
| Sub Title (in English) | |
| Keyword(1) | soft error |
| Keyword(2) | combinational circuit |
| Keyword(3) | logic masking |
| Keyword(4) | fault simulation |
| 1st Author's Name | Yusuke MATSUNAGA |
| 1st Author's Affiliation | Faculty of Information Science and Electorical Engineering, Graduate School of Kyushu University() |
| Date | 2008-10-07 |
| Paper # | SIP2008-116,IE2008-80 |
| Volume (vol) | vol.108 |
| Number (no) | 229 |
| Page | pp.pp.- |
| #Pages | 6 |
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