Presentation 2008-10-30
Demonstration of a Single-Flux-Quantum Floating-Point Divider for the Reconfigurable Data-path
Masamitsu TANAKA, Koji OBATA, Kazuyoshi TAKAGI, Naofumi TAKAGI, Nobuyuki YOSHIKAWA,
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Abstract(in English) We report implementation and experimental results of a single-flux-quantum (SFQ) floating-point serial divider developed for a processor with a reconfigurable data-path (RDP), which we have been studying for an accelerator of large-scale computers. The divider is designed based on a hardware algorithm of division by shift and subtract using the signed-digit representation, and implemented with a regularly aligned pipeline structure called a systolic array. As a result, a high-throughput, low-latency SFQ divider is achieved with a small circuit size. A 4-bit divider has been fabricated using the 2.5-kA/cm^2 niobium process technology, and the successful operations up to 19GHz have been demonstrated.
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Keyword(in English) single-flux-quantum logic / divider / reconfigurable data-path
Paper # SCE2008-27
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Committee SCE
Conference Date 2008/10/23(1days)
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Registration To Superconductive Electronics (SCE)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Demonstration of a Single-Flux-Quantum Floating-Point Divider for the Reconfigurable Data-path
Sub Title (in English)
Keyword(1) single-flux-quantum logic
Keyword(2) divider
Keyword(3) reconfigurable data-path
1st Author's Name Masamitsu TANAKA
1st Author's Affiliation Nagoya University()
2nd Author's Name Koji OBATA
2nd Author's Affiliation Nagoya University
3rd Author's Name Kazuyoshi TAKAGI
3rd Author's Affiliation Nagoya University
4th Author's Name Naofumi TAKAGI
4th Author's Affiliation Nagoya University
5th Author's Name Nobuyuki YOSHIKAWA
5th Author's Affiliation Yokohama National University
Date 2008-10-30
Paper # SCE2008-27
Volume (vol) vol.108
Number (no) 268
Page pp.pp.-
#Pages 5
Date of Issue