Presentation 2008-09-26
Exploration of Input Granularity Optimization for Variable Grain Logic Cell
Masahiro KOGA, Hiroshi MIURA, Motoki AMAGASAKI, Masahiro IIDA, Toshinori SUEYOSHI,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) A Reconfigurable Logic Device (RLD), which has circuit programmability, is applied to embedded systems as a hardware Intellectual Property (IP) core. However, conventional RLDs, which are commercial FieldProgrammable Gate Arrays (FPGAs), cannot achieve efficient implementation. Then, we have studied a reconfigurable logic architecture that has both flexibility and high performance as a reconfigurable IP core. In this paper, we evaluate the granularity of BLE using our technology mapping tool. As a result, best result for area is achieved by 3 inputs BLE, and for logic depth is achieved by 5 inputs BLE.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) reconfigurable IP / coarse-grain / fine-grain / technology mapping
Paper # RECONF2008-33
Date of Issue

Conference Information
Committee RECONF
Conference Date 2008/9/18(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To Reconfigurable Systems (RECONF)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Exploration of Input Granularity Optimization for Variable Grain Logic Cell
Sub Title (in English)
Keyword(1) reconfigurable IP
Keyword(2) coarse-grain
Keyword(3) fine-grain
Keyword(4) technology mapping
1st Author's Name Masahiro KOGA
1st Author's Affiliation Graduate School of Sience and Technology, Kumamoto University()
2nd Author's Name Hiroshi MIURA
2nd Author's Affiliation Graduate School of Sience and Technology, Kumamoto University
3rd Author's Name Motoki AMAGASAKI
3rd Author's Affiliation Graduate School of Sience and Technology, Kumamoto University
4th Author's Name Masahiro IIDA
4th Author's Affiliation Graduate School of Sience and Technology, Kumamoto University
5th Author's Name Toshinori SUEYOSHI
5th Author's Affiliation Graduate School of Sience and Technology, Kumamoto University
Date 2008-09-26
Paper # RECONF2008-33
Volume (vol) vol.108
Number (no) 220
Page pp.pp.-
#Pages 6
Date of Issue