Presentation 2008-09-26
Development of Digit-serial Floating Point Units for Scientific Computation Engine
Taiga BAN, Yuu SHIRAISHI, Kazuya TANIGAWA, Tetsuo HIRONAKA,
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Abstract(in English) We have developed a novel reconfigurable processor with high performance and high precision floating point arithmetic units to accelerate sientific computation. But, it is difficult to implement a lot of high precision floating point arithmetic units on the reconfigurable processor, because the chip area of it's floationg point unit and wiring area to connect these units are extreamly large. Therefore, we developed digit serial floating point arithmetic unit that has a small chip area, and the wiring area to connect these units are also small. In this paper, we shows the effectiveness by the evaluation based on the model of the reconfigurable processor and details of developed floating point arithmetic unit.
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Keyword(in English) digit serial / floating point units / multiple precision
Paper # RECONF2008-32
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Conference Information
Committee RECONF
Conference Date 2008/9/18(1days)
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Paper Information
Registration To Reconfigurable Systems (RECONF)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Development of Digit-serial Floating Point Units for Scientific Computation Engine
Sub Title (in English)
Keyword(1) digit serial
Keyword(2) floating point units
Keyword(3) multiple precision
1st Author's Name Taiga BAN
1st Author's Affiliation ()
2nd Author's Name Yuu SHIRAISHI
2nd Author's Affiliation
3rd Author's Name Kazuya TANIGAWA
3rd Author's Affiliation
4th Author's Name Tetsuo HIRONAKA
4th Author's Affiliation
Date 2008-09-26
Paper # RECONF2008-32
Volume (vol) vol.108
Number (no) 220
Page pp.pp.-
#Pages 6
Date of Issue