| Presentation | 2008-09-26 A measurement of retention time of a dynamic optically reconfigurable gate array with large gates Daisaku SETO, Minoru WATANABE, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recently, various fast reconfigurable devices have been developed. We have been developing a type of such fast reconfigurable devices, Optically Reconfigurable Gate Arrays (ORGAs) that can optically be reconfigured in a perfectly parallel. In this device, large gates can be achieved by exploiting the large storage capacity of a holographic memory. However, the instantaneous performance of ORGAs depends on the actual gate count of its VLSI part. So, we have fabricated the world's largest gate count dynamic optically reconfigurable gate array VLSI (DORGA-VLSI) using dynamic architecture that uses photodiode as memory. This paper presents an estimation result of retention time of the DORGA-VLSI chip. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGAs / Optically Reconfigurable Gate Arrays (ORGAs) / Optical bus / Holographic memories |
| Paper # | RECONF2008-31 |
| Date of Issue |
| Conference Information | |
| Committee | RECONF |
|---|---|
| Conference Date | 2008/9/18(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A measurement of retention time of a dynamic optically reconfigurable gate array with large gates |
| Sub Title (in English) | |
| Keyword(1) | FPGAs |
| Keyword(2) | Optically Reconfigurable Gate Arrays (ORGAs) |
| Keyword(3) | Optical bus |
| Keyword(4) | Holographic memories |
| 1st Author's Name | Daisaku SETO |
| 1st Author's Affiliation | Department of Electrical and Electronic Engineering, Graduate School of Engineering, Shizuoka University() |
| 2nd Author's Name | Minoru WATANABE |
| 2nd Author's Affiliation | Department of Electrical and Electronic Engineering, Faculty of Engineering, Shizuoka University |
| Date | 2008-09-26 |
| Paper # | RECONF2008-31 |
| Volume (vol) | vol.108 |
| Number (no) | 220 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |