| Presentation | 2008-09-12 How to introduce the dynamic key to a provably Secure Block Cipher using FPGA Partial Reconfiguration Kenji Takahashi, Tetsuya Ichikawa, Toru Sorimachi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Cipher circuits are required both to have high security and to show high performance as to circuit scale and processing speed. One way to improve security is to implement various algorithms or many variations of an algorithm on a circuit. In this case, however, the security is achieved at the cost of the performance, that is, the circuit becomes so large that security and performance do not meet. We therefore employ FPGA partial reconfiguration technique and apply dynamic key methods to provably secure block ciphers in order to achieve both security and performance. We choose the 64 bit block cipher MISTY1, realize the dynamic key modification to it in two ways, the partial reconfiguration one and the usual one using selectors, and compare the results. The study finds that it is effective to use the partial reconfiguration when there are four or more circuits to be selected. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Block Cipher / Dynamic Key / Implementation / FPGA / Partial Reconfiguration / Run-time Reconfiguration |
| Paper # | ISEC2008-72 |
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| Conference Information | |
| Committee | ISEC |
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| Conference Date | 2008/9/5(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Information Security (ISEC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | How to introduce the dynamic key to a provably Secure Block Cipher using FPGA Partial Reconfiguration |
| Sub Title (in English) | |
| Keyword(1) | Block Cipher |
| Keyword(2) | Dynamic Key |
| Keyword(3) | Implementation |
| Keyword(4) | FPGA |
| Keyword(5) | Partial Reconfiguration |
| Keyword(6) | Run-time Reconfiguration |
| 1st Author's Name | Kenji Takahashi |
| 1st Author's Affiliation | Mitsubishi Electric Engineering Company Kamakura Office() |
| 2nd Author's Name | Tetsuya Ichikawa |
| 2nd Author's Affiliation | Mitsubishi Electric Engineering Company Kamakura Office |
| 3rd Author's Name | Toru Sorimachi |
| 3rd Author's Affiliation | Mitsubishi Electric Corporation Information Technology R & D Center |
| Date | 2008-09-12 |
| Paper # | ISEC2008-72 |
| Volume (vol) | vol.108 |
| Number (no) | 207 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |