Presentation | 2008/7/29 Timing-Fault-Tolerant Superscalar Processor Ken SUGIMOTO, Hidetsugu IRIE, Masahiro GOSHIMA, Shuichi SAKAI, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | The clock frequency of a microprocessor is generally determined from the timing of its critical path length and the timing margin set by the designers. However, since variations in the manufacturing and operational environments increase, the conventional worst-case design has become unrealistic. Circuit designers are now suffering from the runtime timing-faults because the switching speed of transistors varies unexpectedly widely, and there are researches about detecting and recoverying from runtime timing-faults. Previous researches on recovering from runtime timing-faults are only focus on data-path and do not focus on control-path. In this work, we propose a method which can recover from runtime timing-faults in any place include control-path. In our method, we notice timing-faults along pipeline, and when an instruction retires which may include faults, we reset processor, and do not update architecture state, which is composed of register-file and PC. We implemented a superscalar processor employing this method on a FPGA, and verified that the processor can recover correctly. |
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Paper # | CPSY2008-14 |
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Committee | CPSY |
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Conference Date | 2008/7/29(1days) |
Place (in Japanese) | (See Japanese page) |
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Registration To | Computer Systems (CPSY) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Timing-Fault-Tolerant Superscalar Processor |
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1st Author's Name | Ken SUGIMOTO |
1st Author's Affiliation | Graduate School of Information Science and Technology, The University of Tokyo() |
2nd Author's Name | Hidetsugu IRIE |
2nd Author's Affiliation | Graduate School of Information Science and Technology, The University of Tokyo |
3rd Author's Name | Masahiro GOSHIMA |
3rd Author's Affiliation | Graduate School of Information Science and Technology, The University of Tokyo |
4th Author's Name | Shuichi SAKAI |
4th Author's Affiliation | Graduate School of Information Science and Technology, The University of Tokyo |
Date | 2008/7/29 |
Paper # | CPSY2008-14 |
Volume (vol) | vol.108 |
Number (no) | 180 |
Page | pp.pp.- |
#Pages | 6 |
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