| Presentation | 2008-07-25 Architecture Optimization of a Group Signature Circuit Sumio MORIOKA, Toshinori ARAKI, Toshiyuki ISSHIKI, Satoshi OBANA, Kazue SAKO, Isamu TERANISHI, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Group signature scheme is one of the most active research area in recent cryptographic algorithms/applications. Typical signature algorithm is a combination of dozens of elliptic curve (EC), modular, integer and hash arithmetic operations on data whose bit width exceeds 1,000 bits. A full-H/W IP core is desired for the use of the group signature in SoCs in slow-clock mobile devices. In order to construct a high performance and configurable group signature IP, connecting multiple modular/EC arithmetic units (sub-IPs) and a simple controller not by a wide-band bus but by a narrow-band bus is appropriate. While conventional behavioral synthesis from C-language was used, the development of an additional behavioral synthesizer for parallel scheduling of sub-IP level (C function-library level) operations was necessary. We explored an optimum H/W architecture for a typical group signature algorithm and found that at most 5 modular sub-IPs is enough. Practical H/W speed of less than 0.1 seconds at 100MHz on a 130nm standard cell ASIC library was achieved. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Group Signature / Security H/W / IP core architecture / Behavioral synthesis / C function level parallelism |
| Paper # | ISEC2008-40 |
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| Conference Information | |
| Committee | ISEC |
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| Conference Date | 2008/7/17(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Information Security (ISEC) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Architecture Optimization of a Group Signature Circuit |
| Sub Title (in English) | |
| Keyword(1) | Group Signature |
| Keyword(2) | Security H/W |
| Keyword(3) | IP core architecture |
| Keyword(4) | Behavioral synthesis |
| Keyword(5) | C function level parallelism |
| 1st Author's Name | Sumio MORIOKA |
| 1st Author's Affiliation | Central Research Labs., NEC Corporation() |
| 2nd Author's Name | Toshinori ARAKI |
| 2nd Author's Affiliation | Central Research Labs., NEC Corporation |
| 3rd Author's Name | Toshiyuki ISSHIKI |
| 3rd Author's Affiliation | Central Research Labs., NEC Corporation |
| 4th Author's Name | Satoshi OBANA |
| 4th Author's Affiliation | Central Research Labs., NEC Corporation |
| 5th Author's Name | Kazue SAKO |
| 5th Author's Affiliation | Central Research Labs., NEC Corporation |
| 6th Author's Name | Isamu TERANISHI |
| 6th Author's Affiliation | Central Research Labs., NEC Corporation |
| Date | 2008-07-25 |
| Paper # | ISEC2008-40 |
| Volume (vol) | vol.108 |
| Number (no) | 162 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |