Presentation | 2008-07-24 RTL Design of Parallel FFT with Block Floating Point Arithmetic Hiroshi OCHI, Masayuki KUROSAKI, Leonardo LANANTE, Hendra SETIAWAN, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | In modern wireless communication systems, FFT is one of the key components but requires wide numerical dynamic range. In order to satisfy both requirements of smaller chip size and wider numerical dynamic range, we employ block floating point arithmetic rather than neither fixed point one nor floating point one to implement real systems. In this paper, we show a RTL design result in terms of a radix-4 64-point FFT with parallel architecture using block floating point arithmetic. The results show that we can get more than 100MHz clock frequency with 16-bit length or more even if we make use of FPGA devices. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | FFT / RTL design / Block floating point / Parallel architecture |
Paper # | SIP2008-71,WBS2008-9 |
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Committee | WBS |
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Conference Date | 2008/7/17(1days) |
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Registration To | Wideband System(WBS) |
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Language | ENG |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | RTL Design of Parallel FFT with Block Floating Point Arithmetic |
Sub Title (in English) | |
Keyword(1) | FFT |
Keyword(2) | RTL design |
Keyword(3) | Block floating point |
Keyword(4) | Parallel architecture |
1st Author's Name | Hiroshi OCHI |
1st Author's Affiliation | Kyushu Institute of Technology() |
2nd Author's Name | Masayuki KUROSAKI |
2nd Author's Affiliation | Kyushu Institute of Technology |
3rd Author's Name | Leonardo LANANTE |
3rd Author's Affiliation | Kyushu Institute of Technology |
4th Author's Name | Hendra SETIAWAN |
4th Author's Affiliation | Kyushu Institute of Technology |
Date | 2008-07-24 |
Paper # | SIP2008-71,WBS2008-9 |
Volume (vol) | vol.108 |
Number (no) | 165 |
Page | pp.pp.- |
#Pages | 6 |
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