講演名 | 2008-07-11 24GHz Low Noise Amplifier Design in 65nm CMOS Technology with Inter-Stage Matching Optimization(Session8B: High-Frequency, Photonic and Sensing Devices) , |
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抄録(和) | |
抄録(英) | 2-stage 24GHz low noise amplifier (LNA) was designed using 65nm RF CMOS technology. Since conventional topology with inductive source degeneration provides lower signal gain at 24GHz, a source inductor is eliminated and therefore, modified structure in which a shunt inductor was used for input matching is adopted. Figure of merit (FoM) which includes gain, noise figure, and power consumption was used as a design criterion and was maximized considering various circuit parameters such as transistor channel width of each stage, inductor structure and gate bias voltages. Also, the effect of inter-stage impedance on FoM was analyzed. And for noise simulation, accurate channel thermal noise model was used. Through these steps, FoM of 2-stage LNA was optimized. |
キーワード(和) | |
キーワード(英) | Low noise amplifier (LNA) / CMOS / Figure of merit (FoM) / Inter-stage impedance / Noise figure (NF) |
資料番号 | ED2008-96,SDM2008-115 |
発行日 |
研究会情報 | |
研究会 | ED |
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開催期間 | 2008/7/2(から1日開催) |
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講演論文情報詳細 | |
申込み研究会 | Electron Devices (ED) |
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本文の言語 | ENG |
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サブタイトル(和) | |
タイトル(英) | 24GHz Low Noise Amplifier Design in 65nm CMOS Technology with Inter-Stage Matching Optimization(Session8B: High-Frequency, Photonic and Sensing Devices) |
サブタイトル(和) | |
キーワード(1)(和/英) | / Low noise amplifier (LNA) |
第 1 著者 氏名(和/英) | / Ickhyun SONG |
第 1 著者 所属(和/英) | School of Electrical Engineering and Computer Science, Seoul National University |
発表年月日 | 2008-07-11 |
資料番号 | ED2008-96,SDM2008-115 |
巻番号(vol) | vol.108 |
号番号(no) | 121 |
ページ範囲 | pp.- |
ページ数 | 4 |
発行日 |