講演名 | 2008-07-11 Study on Gate Around Transistor (GAT) Layout for Radiation Hardness(Session9A: Silicon Devices IV) , |
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抄録(和) | |
抄録(英) | We designed a Gate Around Transistor (GAT) layout for radiation hardness. A GAT MOSFET layout with an improved guard ring structure has been fabricated. The Vg-Id and Vd-Id curves are measured before and after exposure to 1Mrad gamma (γ) radiation with a 250krad/hr dose rate. The GAT layout structure shows immunity to radiation. The Vg-Id curve is almost unchanged and leakage current is slightly increased. The effective W/L ratio of the GAT layout is measured and simulated. The GAT layout structure is applied to a source follower schematic. Characteristics of the source follower are measured before and after exposure to 1Mrad gamma (γ) radiation with a 250krad/hr dose rate. Characteristics of the source follower are almost unchanged. A chip was fabricated using commercial 0.35 micron CMOS technology. |
キーワード(和) | |
キーワード(英) | Gate Around Transistor (GAT) layout / Radiation hardness / Radiation Hardening By Design (RHBD) |
資料番号 | ED2008-91,SDM2008-110 |
発行日 |
研究会情報 | |
研究会 | ED |
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開催期間 | 2008/7/2(から1日開催) |
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開催地(英) | |
テーマ(和) | |
テーマ(英) | |
委員長氏名(和) | |
委員長氏名(英) | |
副委員長氏名(和) | |
副委員長氏名(英) | |
幹事氏名(和) | |
幹事氏名(英) | |
幹事補佐氏名(和) | |
幹事補佐氏名(英) |
講演論文情報詳細 | |
申込み研究会 | Electron Devices (ED) |
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本文の言語 | ENG |
タイトル(和) | |
サブタイトル(和) | |
タイトル(英) | Study on Gate Around Transistor (GAT) Layout for Radiation Hardness(Session9A: Silicon Devices IV) |
サブタイトル(和) | |
キーワード(1)(和/英) | / Gate Around Transistor (GAT) layout |
第 1 著者 氏名(和/英) | / Min-Su Lee |
第 1 著者 所属(和/英) | Dept. of Electrical Eng., Korea Advanced Institute of Science and Technology |
発表年月日 | 2008-07-11 |
資料番号 | ED2008-91,SDM2008-110 |
巻番号(vol) | vol.108 |
号番号(no) | 121 |
ページ範囲 | pp.- |
ページ数 | 6 |
発行日 |