Presentation 2008-07-10
3-dimensional Terraced NAND (3D TNAND) Flash Memory(Session4A: Nonvolatile Memory)
Yoon Kim, Gil-Seong Lee, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) We propose a 3-dimensional terraced NAND flash memory. It has a vertical channel so it is possible to make a long enough channel in 1F^2 size. And it has 3-dimensional structure whose channel is connected vertically along with two stairs. So we can obtain high density as in the stacked array structure, without silicon stacking process. We can make NAND flash memory with 3F^2 cell size. Using SILVACO ATLAS simulation, we study terraced NAND flash memory characteristics such as program, erase, and read. Also, its fabrication method is proposed.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) NAND / flash memory / stacked NAND / vertical channel
Paper # ED2008-56,SDM2008-75
Date of Issue

Conference Information
Committee SDM
Conference Date 2008/7/2(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To Silicon Device and Materials (SDM)
Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) 3-dimensional Terraced NAND (3D TNAND) Flash Memory(Session4A: Nonvolatile Memory)
Sub Title (in English)
Keyword(1) NAND
Keyword(2) flash memory
Keyword(3) stacked NAND
Keyword(4) vertical channel
1st Author's Name Yoon Kim
1st Author's Affiliation Inter-university Semiconductor Research Center and School of Electrical Engineering, Seoul National University()
2nd Author's Name Gil-Seong Lee
2nd Author's Affiliation Inter-university Semiconductor Research Center and School of Electrical Engineering, Seoul National University
3rd Author's Name Jong Duk Lee
3rd Author's Affiliation Inter-university Semiconductor Research Center and School of Electrical Engineering, Seoul National University
4th Author's Name Hyungcheol Shin
4th Author's Affiliation Inter-university Semiconductor Research Center and School of Electrical Engineering, Seoul National University
5th Author's Name Byung-Gook Park
5th Author's Affiliation Inter-university Semiconductor Research Center and School of Electrical Engineering, Seoul National University
Date 2008-07-10
Paper # ED2008-56,SDM2008-75
Volume (vol) vol.108
Number (no) 122
Page pp.pp.-
#Pages 4
Date of Issue