Presentation 2008-07-18
A Sub-μs Wake-up Time Power Gating Technique with Bypass Power Line for Rush Current Support
Koichi NAKAYAMA, Ken-ichi KAWASAKI, Tetsuyoshi SHIOTA, Atsuki INOUE,
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Abstract(in English) A sub-μs wake-up power gating technique was developed for low power SOCs. It uses two types of power switches and separated power lines bypassing rush current to suppress power supply voltage fluctuations. We applied this technique to a heterogeneous dual-core microprocessor fabricated in 90nm CMOS technology. When wake-up time on the 2M-gate scale circuit was set to 0.24μs, the supply voltage fluctuation was suppressed to 2.5mV.
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Keyword(in English) stand-by leakage / power gating / wake-up time and rush current noise
Paper # SDM2008-141,ICD2008-51
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Conference Date 2008/7/10(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Sub-μs Wake-up Time Power Gating Technique with Bypass Power Line for Rush Current Support
Sub Title (in English)
Keyword(1) stand-by leakage
Keyword(2) power gating
Keyword(3) wake-up time and rush current noise
1st Author's Name Koichi NAKAYAMA
1st Author's Affiliation Fujitsu Laboratories LTD.()
2nd Author's Name Ken-ichi KAWASAKI
2nd Author's Affiliation Fujitsu Laboratories LTD.
3rd Author's Name Tetsuyoshi SHIOTA
3rd Author's Affiliation Fujitsu Laboratories LTD.
4th Author's Name Atsuki INOUE
4th Author's Affiliation Fujitsu Laboratories LTD.
Date 2008-07-18
Paper # SDM2008-141,ICD2008-51
Volume (vol) vol.108
Number (no) 140
Page pp.pp.-
#Pages 6
Date of Issue