| Presentation | 2008-07-18 Examination of Low-power system LSI architecture by Real time scheduling Yoshikazu Sato, Shigeyoshi Watanabe, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Reduction of power consumption of system LSI with fixed priority scheduling has been described. Scheme of power supply for low-power depends strongly on the scheduling data and each scheduling. The largest reduction of power consumption can be obtained when both supply voltage and frequency can be changed. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | |
| Paper # | SDM2008-140,ICD2008-50 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2008/7/10(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Examination of Low-power system LSI architecture by Real time scheduling |
| Sub Title (in English) | |
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| 1st Author's Name | Yoshikazu Sato |
| 1st Author's Affiliation | Department of Information Science, Shonan Institute of Technology() |
| 2nd Author's Name | Shigeyoshi Watanabe |
| 2nd Author's Affiliation | Department of Information Science, Shonan Institute of Technology |
| Date | 2008-07-18 |
| Paper # | SDM2008-140,ICD2008-50 |
| Volume (vol) | vol.108 |
| Number (no) | 140 |
| Page | pp.pp.- |
| #Pages | 6 |
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