Presentation | 2008-07-17 New design technology of Independent-Gate controlled Stacked type 3D transistor for system LSI Yu HIROSHIMA, Shigeyoshi Watanabe, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | New design technology of Independent-Gate controlled Stacked type 3D transistor has feature of Independent-gate controlled Double-Gate transistor and Stacked type 3D transistor has been proposed. Using New design technology of Independent-Gate controlled Stacked type 3D transistor, pattern area of system LSI designed by cell library can be reduced to 48% compared with that using planar MOSFET. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Independent-gate controlled Double-Gate transistor / Stacked type 3D transistor / logic circuit / system LSI |
Paper # | SDM2008-137,ICD2008-47 |
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Conference Information | |
Committee | ICD |
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Conference Date | 2008/7/10(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Integrated Circuits and Devices (ICD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | New design technology of Independent-Gate controlled Stacked type 3D transistor for system LSI |
Sub Title (in English) | |
Keyword(1) | Independent-gate controlled Double-Gate transistor |
Keyword(2) | Stacked type 3D transistor |
Keyword(3) | logic circuit |
Keyword(4) | system LSI |
1st Author's Name | Yu HIROSHIMA |
1st Author's Affiliation | Graduate School of Electrical and Information Engineering,, Shonan Institute of Technology() |
2nd Author's Name | Shigeyoshi Watanabe |
2nd Author's Affiliation | Graduate School of Electrical and Information Engineering,, Shonan Institute of Technology |
Date | 2008-07-17 |
Paper # | SDM2008-137,ICD2008-47 |
Volume (vol) | vol.108 |
Number (no) | 140 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |