| Presentation | 2008-07-17 Super Chip Technology to Achieve Ultimate Integration Mitsumasa KOYANAGI, Tetsu TANAKA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | As is known as Moore's law, the performance and the packing density of LSI have been rapidly increased owing to scaling down the device size which has been supported by the progress of fabrication process technologies. Various kinds of problems related to device scaling have become tangible as the process technology proceeds to 45nm and 32nm technology nodes. To solve these problems, it is required to develop a new integration technology called "More than Moore" in which the packaging technology, MEMS technology and micro-optics technology are merged to LSI technology in addition to device scaling method. Thus, it is important in the development of future LSI that "More than Moore" technology is in cooperation with "More Moore" technology based on advanced device scaling. The typical example of "More than Moore" technology is a three-dimensional integration technology. We report a new three-dimensional integration technology called a super-chip integration based on a self-assembled wafer bonding. We aim to achieve a ultimate integration by super-chip integration in which various kinds of devices and circuits are integrated into one three-dimensional chip. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Three-Dimensional (3D) LSI / super-chip / wafer bonding / self-organization / self-assembly |
| Paper # | SDM2008-134,ICD2008-44 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2008/7/10(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Super Chip Technology to Achieve Ultimate Integration |
| Sub Title (in English) | |
| Keyword(1) | Three-Dimensional (3D) LSI |
| Keyword(2) | super-chip |
| Keyword(3) | wafer bonding |
| Keyword(4) | self-organization |
| Keyword(5) | self-assembly |
| 1st Author's Name | Mitsumasa KOYANAGI |
| 1st Author's Affiliation | Department of Bioengineering and Robotics, Graduate School of Engineering, Tohoku University() |
| 2nd Author's Name | Tetsu TANAKA |
| 2nd Author's Affiliation | Department of Bioengineering and Robotics, Graduate School of Engineering, Tohoku University |
| Date | 2008-07-17 |
| Paper # | SDM2008-134,ICD2008-44 |
| Volume (vol) | vol.108 |
| Number (no) | 140 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |