| Presentation | 2008-03-28 Learning Algorithm for a Digital Spiking Neuron and Its FPGA Implementation Sho HASHIMOTO, Hiroyuki TORIKAI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The Digital Spiking Neuron is a wired system of shift registers and changes its properties by adjusting the wirings among the registers. In other words, it can easily update its parameter values dynamically, so we propose that we can implement the neuron model on hardware. In this paper, we focus on a learning algorithm for the neuron model, and show some basic results to implement the algorithm by a hardware description language (HDL). In addition, we show experimental measurements by using a field programmable gate array (FPGA). |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Digital spiking neuron / FPGA / Learning / HDL |
| Paper # | NLP2007-177 |
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| Conference Information | |
| Committee | NLP |
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| Conference Date | 2008/3/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Nonlinear Problems (NLP) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Learning Algorithm for a Digital Spiking Neuron and Its FPGA Implementation |
| Sub Title (in English) | |
| Keyword(1) | Digital spiking neuron |
| Keyword(2) | FPGA |
| Keyword(3) | Learning |
| Keyword(4) | HDL |
| 1st Author's Name | Sho HASHIMOTO |
| 1st Author's Affiliation | Dept. of Systems Innovation, Grad. school of Engineering Science, Osaka University() |
| 2nd Author's Name | Hiroyuki TORIKAI |
| 2nd Author's Affiliation | Dept. of Systems Innovation, Grad. school of Engineering Science, Osaka University |
| Date | 2008-03-28 |
| Paper # | NLP2007-177 |
| Volume (vol) | vol.107 |
| Number (no) | 561 |
| Page | pp.pp.- |
| #Pages | 6 |
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