Presentation 2008-03-07
Design of High Density LSI with Three-Dimensional Transistor FinFET : Effect of Pattern Area Reduction with CMOS Cell Library
Keisuke Okamoto, Keisuke Koizumi, Yuu Hirosima, Shigeyoshi Watanabe,
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Abstract(in English) New design method of system LSI with FinFET has been developed. Using planar+FinFET architecture the pattern area of CMOS cell library can be reduced to about 40% compared with the conventional planar case. New design method is a promising candidate for realizing future high performance, high-density system LSI.
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Keyword(in English) system LSI / Three-Dimensional Transistor / FinFET / channel width / sidewall channel width / cell library / TIS
Paper # VLD2007-170,ICD2007-193
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Conference Information
Committee VLD
Conference Date 2008/2/29(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Design of High Density LSI with Three-Dimensional Transistor FinFET : Effect of Pattern Area Reduction with CMOS Cell Library
Sub Title (in English)
Keyword(1) system LSI
Keyword(2) Three-Dimensional Transistor
Keyword(3) FinFET
Keyword(4) channel width
Keyword(5) sidewall channel width
Keyword(6) cell library
Keyword(7) TIS
1st Author's Name Keisuke Okamoto
1st Author's Affiliation Department of Information Science, Shonan Institute of Technology()
2nd Author's Name Keisuke Koizumi
2nd Author's Affiliation Department of Information Science, Shonan Institute of Technology
3rd Author's Name Yuu Hirosima
3rd Author's Affiliation Department of Information Science, Shonan Institute of Technology
4th Author's Name Shigeyoshi Watanabe
4th Author's Affiliation Department of Information Science, Shonan Institute of Technology
Date 2008-03-07
Paper # VLD2007-170,ICD2007-193
Volume (vol) vol.107
Number (no) 508
Page pp.pp.-
#Pages 6
Date of Issue