Presentation 2008-03-07
New design technology of Independent-Gate controlled Stacked type 3D transistor for system LSI
Yu Hiroshima, Keisuke Okamoto, Keisuke Koizumi, Shigeyoshi Watanabe,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) New design technology of Independent-Gate controlled Stacked type 3D transistor has feature of Independent-gate controlled Double-Gate transistor and Stacked type 3D transistor has been proposed. Using New design technology of Independent-Gate controlled Stacked type 3D transistor, pattern area of system LSI designed by cell library can be reduced to 48% compared with that using planar MOSFET.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Independent-gate controlled Double-Gate transistor / Stacked type 3D transistor / logic circuit / system LSI
Paper # VLD2007-169,ICD2007-192
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Conference Information
Committee VLD
Conference Date 2008/2/29(1days)
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Paper Information
Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) New design technology of Independent-Gate controlled Stacked type 3D transistor for system LSI
Sub Title (in English)
Keyword(1) Independent-gate controlled Double-Gate transistor
Keyword(2) Stacked type 3D transistor
Keyword(3) logic circuit
Keyword(4) system LSI
1st Author's Name Yu Hiroshima
1st Author's Affiliation Department of Information Science, Shonan Institute of Technology()
2nd Author's Name Keisuke Okamoto
2nd Author's Affiliation Department of Information Science, Shonan Institute of Technology
3rd Author's Name Keisuke Koizumi
3rd Author's Affiliation Department of Information Science, Shonan Institute of Technology
4th Author's Name Shigeyoshi Watanabe
4th Author's Affiliation Department of Information Science, Shonan Institute of Technology
Date 2008-03-07
Paper # VLD2007-169,ICD2007-192
Volume (vol) vol.107
Number (no) 508
Page pp.pp.-
#Pages 6
Date of Issue