Presentation 2008-03-07
A Circuit Design of Reed-Solomon Decoder using Dynamically Reconfigurable Processor
A. YOSHIDA, Y. HIGASHI, W. MIYAZAKI, T. TANAKA, T. KAMBE,
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Abstract(in English) Reed-Solomon Decoder can correct continues error and it has been a popular technology for various devices such as communication, hard disk, and DVD. This paper, proposes acceleration and reduction of circuit scale of Reed-Solomon Decoder using "Dynamically Reconfigurable Processor" and evaluates its performance.
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Keyword(in English) Reed-Solomon Decoder / Dynamically Reconfigurable Processor / DAPDNA-2 / Cycle based pipelining
Paper # VLD2007-167,ICD2007-190
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Conference Information
Committee VLD
Conference Date 2008/2/29(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Circuit Design of Reed-Solomon Decoder using Dynamically Reconfigurable Processor
Sub Title (in English)
Keyword(1) Reed-Solomon Decoder
Keyword(2) Dynamically Reconfigurable Processor
Keyword(3) DAPDNA-2
Keyword(4) Cycle based pipelining
1st Author's Name A. YOSHIDA
1st Author's Affiliation Department of Electrical and Electric Engineering, Kinki University()
2nd Author's Name Y. HIGASHI
2nd Author's Affiliation Department of Electrical and Electric Engineering, Kinki University
3rd Author's Name W. MIYAZAKI
3rd Author's Affiliation Department of Electrical and Electric Engineering, Kinki University
4th Author's Name T. TANAKA
4th Author's Affiliation Graduate School of Science and Technology, Kinki University
5th Author's Name T. KAMBE
5th Author's Affiliation Department of Electrical and Electric Engineering, Kinki University
Date 2008-03-07
Paper # VLD2007-167,ICD2007-190
Volume (vol) vol.107
Number (no) 508
Page pp.pp.-
#Pages 4
Date of Issue