| Presentation | 2008-03-07 Application-Oriented Dynamic Reconfigurable Network Processor Architecture and Its Optimization Method Motonori OHTA, Shunitsu KOHARA, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we propose an application directional dynamic reconfigurable network processor architecture and its optimization method. The proposed network processor consists of input and output processing processors, application specific hardware and dynamic processors, which could detect the processing bottleneck of each packet when it is executed. Dynamic processor enables throughput improvement of a network processor because dynamic processor executes the highest-load processing selectively so that the bottleneck can be removed. In designing network processors as an actual application, we developed a network simulator in order to obtain the most suitable hardware architecture. By using it, we can evaluate the number of dynamic processors which is the most suitable for a target application. In our work, when we set DES as a target application, we could find that the most suitable number of dynamic processors is six. Furthermore, we presented advantage of application directional dynamic reconfigurable network processor, comparing to the existing products. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Network processor / Dynamic Micro Packet Processor / Network simulator / Encryption ratio |
| Paper # | VLD2007-164,ICD2007-187 |
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| Committee | VLD |
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| Conference Date | 2008/2/29(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Application-Oriented Dynamic Reconfigurable Network Processor Architecture and Its Optimization Method |
| Sub Title (in English) | |
| Keyword(1) | Network processor |
| Keyword(2) | Dynamic Micro Packet Processor |
| Keyword(3) | Network simulator |
| Keyword(4) | Encryption ratio |
| 1st Author's Name | Motonori OHTA |
| 1st Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University() |
| 2nd Author's Name | Shunitsu KOHARA |
| 2nd Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University |
| 3rd Author's Name | Nozomu TOGAWA |
| 3rd Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University |
| 4th Author's Name | Masao YANAGISAWA |
| 4th Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University |
| 5th Author's Name | Tatsuo OHTSUKI |
| 5th Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University |
| Date | 2008-03-07 |
| Paper # | VLD2007-164,ICD2007-187 |
| Volume (vol) | vol.107 |
| Number (no) | 508 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |